Nordic Adds a RISC-V Coprocessor to the nRF54L Line
The nRF54LC10A pairs a 128 MHz Cortex-M33 with a 128 MHz RISC-V coprocessor, 1 MB of non-volatile memory and roughly 30 nanoamps in hibernation, in packages down to 1.93 by 2.29 mm.
Nordic Semiconductor has detailed the nRF54LC10A, a multiprotocol wireless SoC with two 128 MHz cores: an Arm Cortex-M33 and a RISC-V coprocessor. Memory is 1 MB of non-volatile storage and 192 KB of RAM.
Protocol coverage is Bluetooth LE, IEEE 802.15.4 for Thread, Zigbee and Matter, plus proprietary 2.4 GHz modes. Radio current is around 4.0 mA receiving on Bluetooth LE and 5.8 mA transmitting at 0 dBm. Hibernation sits near 30 nA. The operating range is -40 to +85 degrees Celsius. Three packages are offered: CSP29 at 1.93 by 2.29 mm with 12 GPIOs, CSP39 at the same footprint with 20 GPIOs, and QFN48 at 6 by 6 mm with up to 31 GPIOs.
The security list reads like a response to regulation rather than a feature set: Arm TrustZone, secure boot and secure storage, tamper detection, and a cryptographic engine with side-channel protection. For anything that has to clear the EU Cyber Resilience Act, those are no longer differentiators.
The coprocessor is the design change worth thinking about. Protocol handling and sensor servicing can move off the application core, so the main core sleeps more of the time — which is how a battery-powered condition-monitoring node reaches multi-year life without a larger cell. A vibration sensor bolted to a pump motor is not a device anyone wants to revisit annually with a screwdriver.
Early sampling is project-based now, with production expected by the second quarter of 2027. Pricing was not disclosed.
What is not in the announcement is the toolchain question. A second core only helps if partitioning the firmware across it is straightforward, and that depends on what Nordic ships in its SDK rather than on the silicon. Designers who have split work across a network core before will know how much of the benefit is decided there.